Content-addressable memories (CAMs) are hardware search engines that accomplish search-intensive applications faster than algorithmic approaches. Employed as network search engines, CAMs exhibit performance and dynamic power requirements that are driven by their search capability and density, which is predominantly determined by CAM design. Conventional bitwise XOR or NAND/NOR-based CAM static compare architectures (i.e., CAM cell arrays with static compare) are limited in the areas of density, dynamic power and leakage due to cascaded NAND/NOR comparisons and available interconnects within the CAM array. Additionally, the signal integrity of hit bit lines (HBLs) can degrade significantly based on a column data pattern. Dynamic NOR-based shared match line comparison schemes (i.e., CAM cell arrays with dynamic compare) consume large dynamic power in every comparison cycle. This is due to discharging and charging of associated HBLs and rail-to-rail discharge of match lines in every comparison cycle. Improvement in these areas would prove beneficial to the art.